`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	if_id_u(
    input				clk,
    input				rst_n,
    input               flush,
    input				ena,

    input    [63:0]     PC_ifu,
    output   [63:0]     PC_idu,

    input    [31:0]     instr_ifu,
    output   [31:0]     instr_idu

);


pip_reg  #(.N(`DOUBLE_LENTH),.zero(`REGD_ZERO))
u_PC_reg  
    (
        .clk               (clk),
        .rst_n             (rst_n),
        .flush             (flush),
        .ena               (ena),
        .data_i            (PC_ifu),
        .data_o            (PC_idu)
    );

pip_reg  #(.N(`WORD_LENTH),.zero(`REGD_ZERO))
u_instr_reg  
    (
        .clk               (clk),
        .rst_n             (rst_n),
        .flush             (flush),
        .ena               (ena),
        .data_i            (instr_ifu),
        .data_o            (instr_idu)
    );

endmodule